Methods, materials, and equipment useful in chemical-mechanical polishing (CMP) or planarizing of a substrate are highly varied and are used for processing a wide range of substrates having different surfaces and end applications. Substrates that are processed by CMP methods include optical products and semiconductor substrates at any of various stages of fabrication. A wide range of CMP apparatuses, slurries, polishing pads, and methods are well known, with new products being developed on a continuing basis.
Various compositions (also known as polishing slurries, CMP slurries, and CMP compositions) are designed to process (e.g., polish, planarize) a surface of a semiconductor substrate. Some such surfaces contain a metal such as tungsten. A polishing slurry may contain chemical ingredients that are selected specifically for processing a certain type of substrate, such as for polishing a tungsten-containing surface as opposed to a surface that does not contain a metal or that contains a metal different from tungsten. Examples of such chemical ingredients include chemical catalysts, inhibitors, chelating agents, surfactants, oxidants, and others; each of these may be selected to improve desired processing of a metal or non-metal component of a substrate surface. In addition, the polishing composition typically contains abrasive particles. The type of abrasive particles may also be selected based on the type of substrate being processed. Certain types of abrasive particles may be useful in polishing a tungsten-containing substrate surface but may not be useful for processing other CMP substrate surfaces.
Some slurries are designed for processing a surface that is made entirely of a single material, such as a continuous metal or a continuous dielectric material. Other slurries can be designed to process a substrate that has features made from a combination of different materials, e.g., a surface having metal features dispersed throughout a dielectric material.
Methods of polishing tungsten-containing substrates have become important for advanced nodes of semiconductor processing. In steps of preparing tungsten features of a substrate, a starting substrate can include a surface of patterned (non-planar) non-tungsten (e.g., dielectric) material that contains three-dimensional spaces such as channels, holes, gaps, trenches, and the like, that require filling with tungsten. The tungsten can be deposited over the patterned material in a manner to not only fill the spaces, but to also produce a continuous layer of excess tungsten over the discontinuous surface to ensure complete filling of the spaces. The excess tungsten must later be removed to expose a surface of the original patterned material with tungsten features deposited into the spaces between the patterned material.
One example of a substrate that has tungsten (or another metal) features disposed between dielectric features is a semiconductor substrate that includes tungsten “plug” and “interconnect” structures provided between features of dielectric material. To produce such structures, tungsten is applied over a surface that contains a patterned structure made at least in part from dielectric material, e.g., silicon oxide. The patterned dielectric surface is structured, i.e., non-planar, meaning that it includes a surface that is substantially flat or planar except for being interrupted and made discontinuous by the presence of the spaces such as holes, channels, trenches, or the like. When tungsten is applied to the structured dielectric-containing surface, the spaces are filled with the tungsten and a continuous layer of excess tungsten is also formed. A next step is to remove the excess tungsten to expose the underlying dielectric layer and to produce a planar surface of the metal disposed within the spaces of the dielectric material.
By some methods, tungsten is removed in a single step that uncovers the dielectric surface. By other methods, a “two-step” process can be used. In a first step a large portion of the excess tungsten is removed but the dielectric layer is not exposed. This step is commonly referred to as a “bulk” removal step, during which a high tungsten removal rate is desired. A subsequent (second) step can be used to remove a final portion of the remaining tungsten and to eventually expose the underlying dielectric material with tungsten filling the spaces between dielectric features. This step is sometimes referred to as a “polishing” step, wherein a high tungsten removal rate may be important, but wherein other performance requirements are important too.
A polishing step affects both tungsten and dielectric features of a substrate. The end condition of both types of features must exhibit both acceptable planarity and “topography.”
Topography characteristics of a polished substrate include physical phenomena referred to as “erosion” of oxide and “dishing,” of the metal, and their combined effect, which is referred to as “step height.” In one type of pattern, commonly referred to as a line and space (L&S) pattern, the pattern includes line arrays of metal and oxide, such a silicon oxide, in fields of dielectric material such as silicon oxide. The line arrays may be of any density or size, for example alternating 1 micron-wide lines of metal and 1 micron-wide lines of oxide, i.e., a 50% 1 micron array, or alternating lines of different size or density, for example of 1 micron-wide lines of metal and 3 micron-wide lines of oxide, i.e., a 25% 1×3 micron array.
A dielectric field, for comparison, is typically larger in dimension and is comprised of a dielectric material such as a silicon oxide such as TEOS. For example, the field can be a 100 um×100 um area. To evaluate post-polishing pattern performance the absolute oxide loss (material removed) in the field is determined, such as by an optical method using commercially available equipment. The field is used as a reference for the relative pattern measurements of dishing and erosion in the arrays. For example, a 50% 1×1 micron line array comprised of alternating tungsten metal and TEOS oxide lines, can be measured by profilometry or AFM with respect to the field oxide. Erosion is characterized by a difference in the relative height of the oxide, such as the 1 micron TEOS lines, in the line array, as compared to the field oxide. A positive erosion value is interpreted as relative recess of the oxide lines as compared to the field. Metal dishing typically refers to the relative height of the metal lines as compared to the oxide lines in the array. For example in the 50% 1×1 micron line array, a value of 200 Angstroms dishing is interpreted as 200 Angstrom recess of the tungsten lines relative to the oxide lines. Adding the erosion and the dishing provides the total stepheight, in this case from the recessed (dished tungsten) to the field oxide. Total oxide or metal loss in the array can be determined by combining the dishing and erosion values with the absolute oxide loss values determined for the field, as discussed above.
A commercial CMP polishing process can preferably be effective to remove an amount of metal (e.g., tungsten) without producing unacceptable erosion, dishing, or other undesired topography effects at the substrate surface, and with low levels of defects such as scratches and residue.
In view of the above, there is ongoing need in the semiconductor processing industry for a CMP slurry useful for polishing a tungsten-containing substrate, that provides useful or improved performance in areas of: planarity of a polished surface, reduced topography defects including dishing and erosion, and other reduced defects in a polished surface such as reduced scratching and reduced residue, while still providing useful or high removal rates for tungsten and oxide (e.g., TEOS).